To improve the performance of a processing system, an instruction may be simultaneously executed for multiple operands of data in a single instruction period. Such an instruction may be referred to as a Single Instruction, Multiple Data (SIMD) instruction. For example, an eight-channel SIMD execution engine might simultaneously execute an instruction for eight 32-bit operands of data, each operand being mapped to a unique compute channel of the SIMD execution engine. Moreover, one or more flag registers may be used, each flag register having locations associated with each channel of the execution engine (e.g., three eight-bit flag registers could be provided for an eight-channel SIMD execution engine). An ability to efficiently and flexibly access flag register information in different ways may improve the performance of the execution engine.